1. Field of the Invention
This disclosure generally relates to interrupts in computer systems. More specifically, this disclosure relates to techniques for validating message-signaled interrupts that are received from connected devices.
2. Related Art
Recent advances in computational technology have led to improved processor capabilities, increased memory sizes, and increasingly sophisticated storage devices and peripherals. However, as the complexity of computer systems grows, ensuring that different components of a computer system interact as intended becomes more difficult.
For instance, consider the delivery of interrupts from the input/output (I/O) subsystem of a computer system. The time delay associated with delivering an interrupt to a processor, the frequency of interrupts, and the amount of time that the processor spends handling I/O interrupts can have a significant impact on user-perceived application performance. Interrupt-related complexity and delays can be especially apparent in virtualized servers, where many operating systems and applications simultaneously access and/or share hardware. Another set of issues involve erroneous (or malicious) interrupts that do not correctly indicate their source or destination, or create an interrupt load that overwhelms the processing resources assigned to a user.
Hence, what is needed are techniques for validating interrupts without the above-described problems.